by Dr. Dick Walters
Wednesday, October 1, 1997
Abstract
California colleges and universities cannot meet the projected demand for new student enrollment over the next decade by building more classrooms. Alternative forms of instruction must be found. The greatest danger is that the quality of learning may be sacrificed in presenting courses in non-traditional methods, such as Distance Learning.
The greatest need in the learning process is for active, meaningful interaction between learners and with their instructors. We have developed a new tool: Remote Technical Assistance (RTA) that enhances both synchronous and asynchronous interaction between learners and the instructional staff. RTA permits multimedia interaction, file transfer, whiteboarding, and other forms of interaction between pairs or groups, as well as access to course material.
This talk presents the pedagogic rationale behind RTA, describes its operation, and presents a study comparing two courses, one taught in lecture mode, the other in independent study format. The talk will conclude with a summary of collaborative research and learning opportunities in the RTA domain available between CSU Sacramento and UC Davis.
About the Guest Speaker
Dr. Walters is a professor of Computer Science at UC Davis, where he also holds a joint appointment in Medical Informatics in the UCD School of Medicine. He received his Ph.D. from Stanford, and came to UC Davis with the School of Medicine in 1967. In 1983 he moved to the College of Engineering as the first chair of the newly formed Division (now a department) of Computer Science. He returned to full-time teaching and research in 1989. His interests are in distance learning, medical computing, computer support of non-English languages, and database systems.
by Dr. Francisco Corella
Monday, November 3, 1997
Abstract
The term "formal methods", in connection with Computer System Design, refers to a diverse collection of mathematical techniques for specifying computer systems and verifying their correctness and liveness. In a popular technique known as model checking, a property of a design is specified by a formula of a temporal logic, and an automated decision procedure is used to verify that the design, viewed as a Kripke model for the logic, satisfies the formula. In an alternative technique, correctness of a design is stated as a mathematical theorem, which is proved using a partially automated theorem prover.
Formal techniques are being successfully used by the computer industry, and an array of tools are commercially available. However, it is felt that the field of formal methods has not yet realized its full potential. After surveying the main tools and techniques, we will identify the challenges and opportunities that lie ahead for the field.
About the Guest Speaker
Dr. Francisco Corella is a computer architect for Hewlett Packard in Roseville. He received his PhD from the University of Cambridge, England. Prior to joining Hewlett Packard, he was a researcher at Schlumberger and IBM. Dr. Corella's interests include computer architecture, formal methods for computer system design, database and information retrieval systems, decision support systems, and cryptography.
by Dr. Ronald A. Olsson
Wednesday, December 3, 1997
Abstract
The SR language uses a few well-integrated mechanisms for concurrency to provide flexible, yet efficient, support for concurrent programming. This talk introduces the SR concurrent programming language, focusing on its mechanisms for handling invocations.
SR's invocation handling mechanisms, although quite powerful, have significant limitations that make it difficult to solve common programming situations encountered in program visualization, debugging, and some scheduling scenarios. This talk introduces new language mechanisms aimed at remedying these limitations, presents initial performance results, and discusses how the new mechanisms are applicable to other concurrent languages and systems.
The talk also briefly describes some ongoing research projects involving SR and some teaching tools developed for use with SR.
About the Guest Speaker
Dr. Olsson received the Ph.D. degree in computer science from The University of Arizona. He is currently a Professor of computer science at UC Davis and has been Vice Chair of the Department of Computer Science since 1994. His research interests include concurrent programming, programming languages, computer security, verification, systems software, and operating systems. Dr. Olsson has co-authored (with Greg Andrews) the book "The SR Programming Language: Concurrency in Practice".
by Dr. Raju Pandey
Wednesday, Feb. 4, 1998
Abstract
The advent of the Internet and the WWW has revolutionalized the availability of information resources on the Internet. Further, it has fundamentally altered the manner in which such resources are added and made available to end users. This has led to an architecture that is distributed, dynamic, and rapidly evolving. An interesting question is: What kinds of language and runtime supports are needed to facilitate computation within this environment?
In this talk, I will present a model of computation, called mobile computing model, that is ideally suited for computation on the web. The model is location independent and scales well. I will also discuss the various issues that arise in designing an execution environment for mobile programs. I will then present the design of an execution environment that we are implementing at UC Davis. The focus of the design is on developing novel techniques for efficient and secure executions of mobile programs.
About the Guest Speaker
Professor Pandey joined the faculty of the Computer Science department of the University of California, Davis in 1995 after receiving his Ph.D. in Computer Science from the University of Texas at Austin. His dissertation focussed on developing a compositional approach to concurrent programming. He also holds an M.S. in Computer Science from University of Massachusetts, Amherst, and a B.Tech. in Computer Science and Engineering from Indian Institute of Technology, Kharagpur. His research interests are: programming languages, operating systems, parallel and distributed computation, mobile computing, and security.
by Dr. Matt Bishop
Wednesday, April 1, 1998
Abstract
Software vulnerabilities have plagued computer security almost since the first security-related program was written. Currently, they are one of the main reason that computers are considered not secure. The situation is not improving much, either. This talk takes the view that classifying vulnerabilities appropriately and looking for common elements leads to techniques to improve the quality of security-related programs, to detect previously undiscovered vulnerabilities, and to develop tools to aid both these tasks. A case study will be presented, along with a number of techniques for analyzing security-related programs.
About the Guest Speaker
Matt Bishop received his Ph.D. in computer science from Purdue University, where he specialized in computer security, in 1984. He was a research scientist at the Research Institute of Advanced Computer Science and was on the faculty at Dartmouth College before joining the Department of Computer Science at the University of California at Davis. His research areas include computer and network security, especially analysis of vulnerabilities, building tools to detect vulnerabilities, and ameliorating or eliminating them. He also teaches software engineering, machine architecture, operating systems, and (of course) computer security. He has chaired sessions and presented talks and tutorials at numerous conferences, organized and chaired the first two UNIX Security Workshops, and is the program co-chair of the Symposium on Networked and Distributed System Security. He is a member of the Privacy and Security Research Group, which examines issues relating to Internet security.
by Dr. Jozo J. Dujmovic
Department of Computer Science, San Francisco State University
Tuesday, April 21, 1998
Abstract
We present the Logic Scoring of Preference (LSP) method for quantitative evaluation, comparison, and selection of complex systems, and its applications in the area of software evaluation. The evaluation procedure systematically identifies all relevant components for evaluation, individually evaluates each component, and then aggregates all individual evaluation results to generate global indicators of quality of evaluated systems. The parameters of the evaluation model reflect specific requirements of a given user and can be easily modified to reflect a variety of evaluation standpoints. This presentation will include the LSP method and its application for quantitative comparison of windowed environments, including Windows NT, OS/2, Windows 95, NextStep, Windows for Workgroups, and Linux.
About the Guest Speaker
Jozo Dujmovic (BSEE, MS, ScD, University of Belgrade) is Professor of Computer Science at San Francisco State University. His teaching and research activities are in the areas of software engineering and computer performance evaluation. He is the author of more than 100 publications and a Senior Member of IEEE.
by Dr. Biswanath Mukherjee
Department of Computer Science, University of California at Davis
Wednesday, September 2, 1998
Abstract
As our appetite for network bandwidth continues to escalate, what are the corresponding technological limits and research challenges? While fiber bandwidth can approach nearly 50 terabits per second (Tbps), our electronic speeds are limited to a few tens of gigabits per second (Gbps). Fortunately, this bandwidth mismatch can be effectively exploited by wavelength-division multiplexing (WDM), and several prototype WDM networks are under development.
While optical communication technology has been a curiosity for a long time, optical network architectures have been researched for the past 10 years or so. In this talk I will chart the progress of the optical networking field over this period; and examine current research, development, and standardization efforts. Then, I will present my views on how we networking researchers can keep pace with this fast-moving field, and outline a sampling of important optical networking research problems that we as can effectively contribute towards.
I will spend the final 10 minutes of this talk to discuss the graduate and research programs/opportunities in computer science at UC Davis for recruiting potential MS/PhD students.
About the Guest Speaker
Biswanath Mukherjee is Professor and Chair of Computer Science at UC Davis. He received his PhD in EE from University of Washington, Seattle, in 1987, and the bachelor's degree in electronics from Indian Institute of Technology, Kharagpur, India, in 1980. His interests include lightwave networks, network security, and wireless networks.
by Todd Heberlein
Net Squared, Inc.
Wednesday, October 7, 1998
Abstract
Intrusion Detection is a relatively young field, beginning only about fifteen years ago. However, during this short time, the field has gone through several transitions. During my talk, I will cover some the technical, perceptual, and economic changes that have occurred through the years, and I will discuss some of the factors which may be catalysts for changes in the future.
About the Guest Speaker
Mr. Heberlein is Net Squared's president and principal researcher. He received a Masters in Computer Science from UC Davis in 1991, where his research was concerned with the detection of intrusive activity in computer systems by analyzing network traffic. He was the chief architect and developer of the Network Security Monitor (NSM), which continues to be used and enhanced by Lawrence Livermore National Laboratory under the name Network Intrusion Detector (NID) and the US Air Force as part of the Automated Security Incident Measurement (ASIM) project. He was also a principal developer of the US Air Force's Distributed Intrusion Detection Systems (DIDS) project, and has recently investigated intrusion detection for very large networks for DARPA. Mr. Heberlein also enjoys studying the fundamental nature of vulnerabilities. He has authored or co-authored numerous papers on intrusion detection in general and network-based intrusion detection in particular. He has given tutorials on intrusion detection for the 1993 IEEE GlobeCom conference in Orlando, the 1994 Computer Security Applications Conference in Orlando, and the 1996 LISA Conference in Chicago.
by Dr. Venkatesh Akella
Department of Electrical and Computer Engineering, University of California at Davis.
Wednesday, November 25, 1998
Abstract
The question that will be addressed in this talk is: How should software be designed in the next decade? Businesses are increasingly relying on information technology to reduce costs and to enhance productivity. Reducing development time and evolutionary design of software are becoming increasingly important. One idea that is being tossed around is component-based software design. This idea is reminiscent of hardware design. Complex software would be built by assembling (or wiring) pre-existing software components, just as a hardware system is built by wiring a set of ICs (integrated circuits) in sockets on a printed circuit board. Sounds good. But, is that REALLY possible? What are the core issues in component-based design both from a technical perspective and a business perspective? What are the possible solutions in the horizon? We will examine these questions by taking a closer look at Microsoft's Component Object Model (COM) and Sun Microsystems's JavaBeans initiative.
About the Guest Speaker
Venkatesh Akella received a Ph.D. in Computer Science from the University of Utah in 1992 and is currently an Associate Professor of Electrical & Computer Engineering at the UC Davis. He received National Science Foundation's CAREER Award in 1997. His research interests are asynchronous logic, computer architecture, and software engineering.
by Lee Kercher
Department of Information Technology, State of California.
Wednesday, December 2, 1998
Abstract
Discuss the nature of Y2K problems, from application systems to desktops to embedded processors, and the potential impacts of those problems. Review the efforts for identification and remediation to date, with lessons learned, progress made and tasks remaining. Summarize related issues of legal liability, contracting, procurement and politics. Attempt predictions of activities and complications during the remainder of the pre-failure period, and preparations and expectations for 2000.
About the Guest Speaker
Mr. Lee Kercher is currently the Deputy Director for Technology and Infrastructure at the California State Department of Information Technology, where he is responsible for policy related to the management of the California state governments technology infrastructure. Specific responsibilities include telecommunications networks, data centers, new technology, systems management, operational recovery and information security. He has 18 years experience in data processing positions with the State of California and has worked in a variety of management assignments related to computer networking, including planning, design and operations. Mr. Kercher has extensive experience in data center operations, including his most recent prior position as Assistant Director for Operations of Californiams Teale Data Center. His responsibilities in that position included the establishment of the data centerms Year 2000 effort.
by Mick Fandrich
Intel Corporation, Folsom
Wednesday, February 3, 1999
Abstract
Semiconductor design has always been about "abstraction" - taking an abstract concept and turning it into something physical. As technology has progressed, Computer-aided Design tools have been developed to help deal with the complexities. As new hurdles develop, new abstractions are developed to deal with them, and new CAD tools are developed. This increase of abstractions and associated tools has lead to an explosive increase in data storage requirements, with hundreds of thousands of files and hundreds of gigabytes of data required for a single design. Even more problematic is maintaining "synchronization" between the many design abstractions, causing re-work and a significant loss in productivity. Typical management solutions have included meetings, meetings, and more meetings, followed by team management restructuring. However, application of Information Science techniques to these problems hold promise for reducing file explosion and controlling abstraction synchronization. Information flow analysis, data modeling, and relational databases are typically associated with business processes, but may be equally applicable to complex design processes. There is hope for reducing the chaos.
About the Guest Speaker
Mick Fandrich joined Intel Corporation upon completion of his degree in Engineering Technology from Devry Institute of Technology in 1980. During his tenure at Intel, Mick has held design positions in the Microcontroller and Flash Memory divisions. He is author and co-author of 37 patents in thearea of Write Automation for Flash Memories. Mick currently holds the position of Design Automation manger for the Flash Products Division. He and his staff are chartered with developing a highly productive design environment for 100 designers. Mick serves on the Technical Board of Directors for Antrim Design Systems, Inc., and is First Vice President on the Board of Directors of the Sacramento Youth Symphony. In his spare moments, Mick enjoys collecting and playing musical instruments, and developing database applications for the Youth Symphony.
Component Architectures and Frameworks
by Dr. Thomas P. Vayda
Platinum Technology International Inc.
Wednesday, March 24, 1999
Abstract
This presentation provides an overview of the development of large scale software systems using component based technology. It covers current practices today and upcoming trends for the next millennium. Currently there is an evolution from Object-Oriented to Component Based Development. Even with the adoption of these two promising approaches, designing high-performance, large scale, distributed systems, and rapid application development (RAD) through effective reuse have proven to be more difficult than expected; pragmatic, enterprise scale solutions still remain to be developed. This presentation describes solid foundations and pragmatic approaches for attacking these problems including new techniques for large scale reuse through the use of instantiable component frameworks. It focuses on many of the key issues in an integrated manner: distributed component architectures, component based modeling and development techniques, solid development processes based on a reuse foundation, effective use of patterns and pattern instances and integrated tool suites. The attendees will gain a clear understanding of the issues that need to be addressed and some directions for pragmatic solutions.
About the Guest Speaker
Thomas P. Vayda, Ph.D., is the Chief Technology Officer of Platinum Global Consulting and Professor of Computer Science at California State University, Chico. As CTO, he is responsible for providing technological direction in requirements specification architecture, analysis, design, implementation and testing of large scale distributed Object-Oriented/Component based client/server systems and specifying and applying effective software development processes. Dr. Vayda is an internationally recognized expert, makes frequent presentations at domestic and international conferences on Object Technology, Large Scale Architecture and Project Management and writes a column for Component Strategies. He has over 30 years of pragmatic IT and Computer Science experience, has founded successful companies and holds a Ph.D. in Computer Science from the University of California, Davis.
by Dr. Youwen Ouyang
California State University San Marcos
Wednesday, May 5, 1999
Abstract
Challenges for successful reuse include populating the repository with the right type of components, representing and organizing the components in a way that the components are easy to be retrieved, and providing mechanisms to compare the candidate components with the requirement of the new component and to assist adaptation. The Requirement Reusability Model (RRM) is developed to capture the aspect of reuse that a component can be constructed by modifying another component. The inspiration of the model is data mining where statistical analyses are performed to identify patterns that are otherwise hidden and to reveal potential of reusability.
There are two major phases in RRM. At the Reusability Analysis (RA) phase, a measurement space is defined to represent the functional semantics of the components based on the formal specifications of the components. Clustering analysis is employed to group the components that are similar in function into the same clusters. At the Reusability Realization (RR) phase, the generic requirements for clusters are automatically extracted to create reusable frameworks for the clusters. The frameworks created are useful for constructing the implementation of individual transactions in the same cluster. Guidelines for adaptation from the frameworks to actual implementation are also provided.
An automated system, called REST (a Reusers^R assiSTant) implements RRM. The input to REST is the specification of a relational database system. Based on the input, REST produces a repository of reusable frameworks. The products of REST also include a data dictionary and a transaction dictionary. Each entry of the transaction dictionary indicates the name of a transaction, the description of the functional semantics of the transaction, the cluster to which the transaction belongs, and a suggested framework to be reused for the implementation of the transaction.
About the Guest Speaker
Dr. Ouyang received her Ph.D. degree in Computer Science from Louisiana State University, Baton Rouge, in 1996. Currently, she is an assistant professor in Dept. of Computer Science, CSU at San Marcos. Her research interests include: software reusability, reengineering, object technology, database systems, industrial applications of formal methods.
by Dr. Ratan Nalumasu
Hewlett-Packard, Cupertino, CA
Wednesday, September 1, 1999
Abstract
Due to the increasing complexity of the modern modern digital systems formal verification has recently gained considerable attention. In the first half of the talk, I will introduce various verification techniques and how they can be used in various phases of a design. In the second half of the talk, I will present how formal verification can be used in designing a shared memory system. These systems require that the system architect address correctness issues at many levels. I will introduce some of these levels, and then take an in-depth look at a high-level correctness issue: does the system correctly implement sequential consistency. The approach, called test model checking, is ideally suited for application in an industrial setting as it is a light-weight "simulation" technique and is a "black-box" approach where the testing environment need not change even when the underlying hardware dramatically changes.
About the Guest Speaker
Ratan Nalumasu received his bachelor's degree in Computer Science from Regional Engineering College, Warangal, India in 1992. He received Ph.D. from Dept of Computer Science, Univ. of Utah in 1998. For the past one year he has been working at HP, Cupertino where he applies formal verification to the high-end and mid-range chipset designs. His primary interests are formal verification and multiprocessor systems.
by Dr. Chuck Schneebeck
Sonoma State University
Wednesday, October 6, 1999
Abstract
This presentation will describe the work that the Center for Distributed Learning (CDL) is doing to address some of the barriers to distributed learning. Partnerships with the private sector and with other state systems will be described. Simulations that are being created at the CDL will be demonstrated. The work the CDL is doing to create online learning and teaching communities will also be discussed.
About the Guest Speaker
Chuck Schneebeck is Director of the California State University Center for Distributed Learning, an operation of the CSU Office of the Chancellor. He was previously Director of Academic Computing at California State University at Long Beach and at Fullerton College. Prior to entering the technology arena, he taught chemistry and biology for twenty-one years.
by John Thomas Flynn
Litton PRC
Wednesday, November 3, 1999
Abstract
A relatively new phenomenon, following private sector trends of over a decade, is the creation of the public sector CIO position. More often than not, this position is created as a result of a public relations disaster caused by the failure of a major systems integration effort. However, the duties and responsibilities of the new CIO are created at the expense of the current bureaucracy's fractured, autonomous, and turf-conscience agencies. In addition, the preponderance of funding for many of the state's largest IT efforts comes from the federal government whose role has very often made IT failure more likely. And finally, in the fish bowl of local politics, there are significant disincentives to meaningful reform. This presentation will highlight these and other challenges of the public sector CIO and lay out a strategy to build an environment for successful application of information technology.
About the Guest Speaker
John Thomas Flynn became Vice President for Litton PRC in January 1999 where he is responsible for directing the strategic development of this billion-dollar technology company's public sector business for state and local government. Prior to PRC he was the State of California's first chief information officer having been appointed by Governor Pete Wilson in 1995 to oversee the state's $2 billion annual investment in information technology and telecommunications (IT/TC). Mr. Flynn directed the Department of Information Technology, a new, cabinet-level agency reporting directly to the Governor. In addition, he became California's Year 2000 czar, responsible for coordinating the state remediation of its 3,000 computer systems. The State of California is comparatively a Fortune 5 organization with revenues in excess of $125 billion annually. Prior to coming to California, Mr. Flynn was selected by Governor Weld to be Massachusetts' first chief information officer in 1994. He is immediate past President of the National Association of State Chief Information Officers (NASIRE) which represents the CIO's from the 50 states, six U.S. territories, and DC. Mr. Flynn serves on several boards including: the U. S. General Accounting Office, the Fisher Center for Management and Information Technology, Walter A. Haas School of Business at the University of California, Berkeley, and several IT start-up companies. Mr. Flynn was a White House Appointee of President Ronald Reagan serving executive director of the Federal Regional Council, a White House intergovernmental coordinating committee, in 1982; and during President Reagan's second term he was appointed New England Regional Director of the U.S. Department of Labor. Prior to joining state government, and his service as a White House appointee, he spent nearly 15 years in computer systems development primarily responsible for the design and implementation of large financial and statistical applications in both public and private sector environments. Mr. Flynn taught at the Northeastern University Graduate Business School in the Entrepreneurial Studies Program from 1984 to 1995, and was a member of the faculty at Emmanuel College in Boston, Massachusetts. In addition, he was a member of the Advisory Council of the Suffolk University School of Management's Computer Information Systems Department.
by Dr. Jonathan Lee
Boston University
Wednesday, Feb. 9, 2000
Abstract of Two Talks
Molecular Mechanistic Studies in Alzheimer's Disease: The formation of amyloid deposits is a key event in the pathogenesis of Alzheimer's Disease. For nearly 100 years the precise molecular mechanism of pathogenesis has remained a mystery. Very recently several key mechanisitic features have been revealed, and the stage in now set to address the issue of a biochemical target. Biochemical results will be presented on how amyloid deposits are formed, as well as what types of therapeutic intervention may be reasonable.
First Contacts in Disordered Space & Pathogenic Contacts in Alzheimer's Disease: This is a two part lecture. The first theme addresses the nature of the reagent in a protein folding reaction. Unfolded proteins are often highly disordered, but very very non-random. Moreover, commonplace references to "random coils" are not only inaccurate, but these references often seriously mislead the uninitiated. Experimental results which begin to define the structural rules for the disordered space will be presented. The second theme addresses the beta sheet structure of Alzheimer's disease amyloid fibrils. By taking advantage of the protein structure data bases, it is now possible to make reasonable predictions on strand pairings in beta sheets. With these predictions in hand, the ensemble of several thousand theoretical beta strand pairings can be seriously reduced. Data from these studies can in turn be used to resolve the liklihood of currently proposed structural models, as well as provide the foundation for new structural models. Combined with chemical analysis of fibril structure, it is now clear that if we are to accommodate all of the available experimental data, then a new model is necessary.
About the Guest Speaker
Dr. Jonathan Lee is a Assistant Professor of Chemistry Department at Boston University. He received his Ph.D. from the Ohio State University in 1986. He also had NIH Fellowship at Harvard Medical School 1991-1993. His current research includes: a)the human b-amyloid peptide found in Alzheimer's disease, and b) a regulatory molecule (p56lck) implicated in the signal trasduction pathway that is part of the activation cascade found within the T-cells of the immune system.
by Dr. Micheal Gertz
University of California Davis
Wednesday, March 1, 2000
Abstract
The World Wide Web can be considered as the largest information repository. Its steady growth and diversity, however, make it more and more difficult for users not only to find information they are interested in, but also to organize (references to) information of interest in a uniform and meaningful way. Domain specific Web Sites or simple collections of bookmarks do not solve the problem since they only provide a collection of links organized according to some fixed taxonomy.
In this talk I will give an overview of an approach that tries to alleviate the above problems by using domain specific ontologies and data annotation techniques. The core idea of the approach is to build and use ontologies for conceptualizing domain specific concepts (knowledge) and relationships among concepts. Contextual information represented in an ontology is used to annotate (remote) information represented on the Web. Annotations, as semantic carrying metadata, can be associated with Web-based information at different levels of granularity, ranging from complete Web sites to specific portions of a Web page. Both the modeling of an ontology and the annotation of data residing at Web sites is based on using modeling constructs provided by XML and associated concepts, e.g., XLink. For querying and retrieving information of interest, a domain specific ontology then is used as a uniform and semantic rich repository of links to and among diverse types of Web based information sources.
About the Guest Speaker
Dr. Gertz received his Ph.D. in Computer Science from the University of Hannover, Germany, in 1996, and is currently an Assistant Professor in the Department of Computer Science at the University of California at Davis. His current research interests include federated, distributed and multidatabase systems with a particular focus on data integration techniques, database interoperability, and the management of data quality and integrity. Dr. Gertz's research interests also includes security in database and information systems with an emphasis on secure data mediation and the discovery of security policies.
by Dr. Mohammad H. Heydari
James Madison University
Thursday, March 30, 2000
Abstract
This is a joint work with: Dr. Hal Sudborough, University of Texas at Dallas. The n-dimensional Pancake Network, Pn, has processors labeled with each of the n! distinct permutations of length n and a connection between two processors when the label of one is obtained from the other by some prefix reversal. Each permutation is considered as a stack of different size pancakes. The well known Pancake Problem concerns the number, f(n), of prefix reversals required to sort n pancakes. We describe a 9(n+2)/8 step sorting sequence for Gates and Papadimitriou's stack of n pancakes, Xn, used for establishing their lower bound, thus disproving the conjecture that 19n/16 steps are required. Furthermore, We improve their lower bound by showing f(n) <= 15n/14 (<=: less than or equal to). In fact, we define for each n = 0 (mod 14) a stack of pancakes, Yn, and show that 15n/14 <= f(Yn) <= 8(n-1)/7. We show that -In, the conjectured hardest stack of burnt pancakes, can be sorted in 3(n+1)/2 steps, for all n = 3(mod 4) and n <= 23. If -In is indeed hardest, this implies that both the ``burnt'' and ``unburnt'' pancake networks of dimension n have diameter at most 3(n+1)/2. Values of f(n), for n <= 11, were given previously. We note that f(12) = 14, f(13) = 15, and f(19) >= 22.
About the Guest Speaker
Dr. Mohammad H. Heydari is Associate Professor at the Department of Computer Science, James Madison University. He received his Ph.D. in Computer Science, University of Texas at Dallas, Richardson, August 1993. Before joining James Madison University, he was Associate Professor of University of Wisconsin-whitewater, 1993-1995; Assistant Professor of Jackson State University, Jackson, MS, 1984-1986; and Software Engineer of Scientific Machines Corporation, Dallas, TX, 1981-1984. His research interests include interconnection networks and parallel architectures, telecommunication networks, e-commerce, VLSI layout and routing, and software engineering.
by Markus Levy
EEMBC
Wednesday, April 5, 2000
Abstract
The EDN Embedded Microprocessor Benchmark Consortium (EEMBC, pronounced like "embassy") embarked on a mission in April 1997 to turn the art of embedded-processor benchmarks into a science. As a result, you can now more easily obtain an accurate, reliable, and application-based metric to evaluate a processor's performance. EEMBC's suites of benchmarks reflect real-world applications. The consortium's general strategy is to extract the processor-intensive code segments of the most popular embedded applications. This method allows you to choose the benchmarks that are relevant to the application for which you are designing, rather than benchmarks that attempt to lump results into a single number. To accomplish this task, the members (comprised of 37 of the industry's largest semiconductor, intellectual property, compiler, and RTOS firms) first established separate subcommittees that target each of the primary vertical-market segments: automotive/ industrial, consumer, networking, office automation, and telecommunications. Each subcommittee then selected the applications within its corresponding market segment; these applications include engine control, digital cameras, printers, cellular phones, modems, and more. EEMBC's members then dissected each of the applications and derived 35 algorithms to develop for the consortium's initial benchmark suites. (For a list of EEMBC's Phase I benchmarks, go to www.eembc.org.) These benchmarks allow you to pick the ones that most closely resemble your application. Unlike synthetic benchmarks, these are real algorithms in real embedded applications.
About the Guest Speaker
Mr. Markus Levy is the President of EEMBC. Mr. Levy is a Technical Editor for EDN Magazine responsible for the coverage of microprocessors, microcontrollers, digital signal processors and embedded development tools. He has served in this position for five years. He is also the President of the EEMBC Certification Lab. He is the author of a technical reference manual, "Designing with Flash Memory". Prior to employment at EDN, Mr. Levy had worked for Intel Corporation for approximately seven years, holding several different positions and obtaining several patents. These positions included Technical Customer Training for microprocessor products and development tools, and Technical Marketing and Applications for Flash Memory products.
by Dr. James Kho
California State University Sacramento
Wednesday, April 26, 2000
Abstract
The CSU is embarking on a long-term large scale project to implement a state of the art, integrated information system. The target administrative environment is for all 23 campuses to perform administrative functions, initially including human resources, financials, and student services, in concert with a common suite of applications software. Estimated at $300 million over 5 to 7 years, it will likely be the most expensive CSU undertaking to date. As a multi-faceted initiative, this requires participation of all levels of campus management and staff, and must integrate with the plans of the CSU that affect campus operations and budgeting. The talk will cover the design of the CSU baseline prototype, and the approach used to develop, implement, and integrate cross functional modules.
About the Guest Speaker
Dr. James Kho serves on the CSU Common Management System Board and chairs the Sacramento campus Implementation Steering Committee. He is a former Chair of the CSUS Computer Science Department and the immediate past Associate Dean of the College of Engineering and Computer Science. Dr. Kho presently serves as the university's Associate Vice President for Administration.
by Dr. Matthew Farrens
University of California Davis
Wednesday, September 27, 2000
Abstract
Processor architectures of the future face several design challenges that require a re-examination of traditional methods. Increasing transistor densities widen the gap between processor cycle time and relative memory access time, while distributing a high-speed synchronous clock to billions of transistors is prohibitively difficult and expensive. Furthermore, as processors become more complex and compiler analysis becomes more intelligent, their interface must be improved to expose the strengths of both. The focus of the research presented in this talk is on solving these problems using a distributed, decentralized (DD) approach to computing. The underlying processor model used is both distributed and decentralized in resource allocation, consisting of multiple independently programmable processing elements, elastically connected to one another and to memory via FIFO queues. This DD approach is capable of tolerating memory latency, overcoming the clock distribution problem, and facilitating the transfer of compiler information to the underlying hardware. This talk will focus on Decoupled Architectures, a particular type of DD architecture.
About the Guest Speaker
Professor Farrens received his Ph.D. from the University of Wisconsin in 1989, and has been a professor at UC-Davis since that time. He was awarded the NSF Young Investigator Award in 1991, and has been very active in the professional community (Chair of the IEEE Technical Committee on Microarchitecture, program chair of Micro27, multiple program committees, etc.) His primary area of interest is in high performance computer architectures.
by Dr. Jean-Pierre R. Bayard
California State University Sacramento
Wednesday, November 8, 2000
Abstract
This presentation summarizes the findings from a year-long research project undertaken at the National Institute for Science Education located at the University of Wisconsin-Madison. The project sought to identify key effects of computers on the instruction of mathematics, sciences, engineering and technology. Following a brief description of the research method used by the Institute, a sample of the cases will be presented outlining the context, problems, strategies and results that instructors in sciences, math, engineering and technology at a variety of institutions nationwide have experienced in implementing inquiry-based reform in their curriculum.
About the Guest Speaker
Jean-Pierre R. Bayard was born in Port-au-Prince, Haiti on January 9, 1962. In 1980, he became an undergraduate student at the University of Massachusetts, Amherst. He received his Bachelor, Masters and Ph.D. degrees from that institution in 1984, 1986, and 1990, respectively. His doctoral research work focused on the transient responses of dipole arrays, and the application of the finite difference method to the modeling of microstrip arrays. In September of 1990, he joined California State University, Sacramento, as an assistant professor in the Department of Electrical & Electronic Engineering. Jean-Pierre's research interests are in the numerical modeling and experimental applications of microwave printed antenna elements and arrays. On the one hand, he has published several journal articles describing the performance of arrays of dipoles printed on dielectric substrates protruding from a ground plane. One the other hand, he has worked on several grants (sponsored by the California Department of Transportation) designing microwave systems for the automation of passenger and maintenance vehicles. In the area of teaching, Jean-Pierre's interests are in the use of technology in the teaching and learning of engineering. Over the past six years, he has developed multimedia notes and interactive leaning and assessment modules for several electrical engineering courses. Jean-Pierre believes that technology-mediated instruction, whether it is in the form of television or the worldwide web, is a valuable partner of the traditional classroom teaching, all working toward an enriched learning environment. His leadership in this area earned him the Outstanding Teaching Award for the CSUS College of Engineering and Computer Science for the 1997-1998 academic year. He has also been named the outstanding Electrical & Electronic Engineering faculty in 1996 and 1998. This year he is a fellow of the NSF-funded National Institute for Science Education (NISE). In that capacity he is investigating the use of computer-based technology in the teaching of sciences, mathematics, engineering and technology.
by Dr. Kwan-Liu Ma
University of California, Davis
Wednesday, Feb. 7, 2001
Abstract
Leading-edge scientific computations with demanding memory and processing requirements are being performed on massively parallel supercomputers. Examples include many grand challenge problems studied under the HPCC programs, and the unprecedented complexity and size of the problems tackled by DOE's Accelerated Strategic Computing Initiative (ASCI) program. To support applications which use the new generation of massively parallel supercomputers such as those ASCI-class machines, visualization tools appropriate to the parallel architecture must be developed and used either as a runtime process to provide immediate visual feedback from large-scale simulations, or as a postprocess to perform more in-depth exploration of the data at the highest possible resolution.
Modeling of 3-d physical phenomena often results in volume data. Rendering volume data can be as expensive as the numerical simulations generating the volume data. While new generation of graphics hardware can be used to render volume data directly. Interactive visualization of large-scale volume data must use a parallel computer.
I will describe two basic parallel volume rendering algorithms. One algorithm designed for rendering regular-grid data is based on a clever image compositing algorithm maximizing processor utilization. The other for rendering unstructured-grid data, aims at achieving the highest possible flexibility and scalability. Good scalability is achieved by overlapping communication as much as possible with computation and by a static load distribution technique. Test results on the various parallel architectures will be presented.
About the Guest Speaker
Kwan-Liu Ma is an associate professor of computer science at the University of California, Davis, where he teachs and conducts research in the area of computer graphics and scientific visualization. His career research goal is to improve the overall experience and performance of data visualization through more effective user interface designs, interaction techniques, and high-performance computing. Ma received his PhD from the University of Utah in 1993. He recently received the prestigious PECASE (Presidential Early Career Award for Scientists and Engineers) award. He served as co-chair for the 1997 IEEE Symposium on Parallel Rendering, the IEEE Visualization Conference Case Studies in 1998 and 1999, and the first NSF/DOE Workshop on Large-Scale Data Visualization. He is currently editing a special issue of IEEE Computer Graphics and Applications on Large Scale Data Visualization.
by John Owens
Stanford University
Wednesday, March 7, 2001
Abstract
The Imagine Stream processor is a high-performance, power-efficient, programmable signal and image processor that achieves the performance density of special-purpose processors. This talk will highlight the key features of the Imagine Stream Architecture: large amounts of available arithmetic bandwidth, an area-efficient and power-efficient stream register organization, and a data bandwidth hierarchy which effectively manages data communication. By casting media applications into the stream programming model, they are able to take advantage of these architecture characteristics.
A prototype Imagine stream processor being designed at Stanford is targeted to operate at 500MHz with a die size of less than 1cm^2 when fabricated in a 0.15 micron process. With a peak performance of 20 GFLOPs on floating-point applications and over 40 GOPS on integer applications, a single Imagine processor sustains 19.2 GOPS on MPEG encoding. Other media applications perform similarly. This significantly outperforms modern high-performance processors and digital signal rocessors, while achieving power efficiencies competitive with special-purpose embedded processors.
About the Guest Speaker
John Owens is a Ph.D. student in Electrical Engineering at Stanford University. He is one of the architects of the Imagine stream processor and is coadvised by Bill Dally and Pat Hanrahan. He previously worked on the Lightning distributed framebuffer at Stanford, consulted at Interval Research Corporation, and has interned at SGI, Intel, Sun, and Oracle. John has a BS in EECS from the University of California, Berkeley (1995), a MS in EE from Stanford (1997), and hopes to graduate this year.
by Dr. Donghui Wu
Clickstream Intelligence, Oracle Corporation
Wednesday, September 26, 2001
Abstract
Support Vector Machine (SVM) is a general learning system based on recent advances in statistical learning theory. SVM is invented by Valdmir Vapnik, and based on Structural Risk Minimization (SRM) principle and VC dimension. Since its introduction in earlier 1990s, SVMs have been well received by machine learning and data mining community, been extensively studied, and applied to a broad array of application fields. SVMs deliver state-of-the-art performance in real world applications such as text categorization, hand-written character recognition, image classification, bioinformatics, etc. SVM has established itself, along with neural networks and decision trees, as one of the standard tools for machine learning and data mining.
In this talk a brief introduce to the theory and various formulations of Support Vector Machines will be given. Multiple extensions of standard SVMs will also be discussed. In addition, several applications of SVMs will be presented and compared with other machine learning and data mining methods.
About the Guest Speaker
Donghui Wu is currently a Senior Member of Technical Staff at Oracle Corporation, Clickstream Intelligence Group. Prior to joining Oracle, he was an analyst at United Airlines Research Center, where he worked on various airline operations related data mining tasks. His research interest includes Web Mining, Text Mining, Highly Dependent Data Mining, Database Marketing, Decision Trees, Support Vector Machines, and Mathematical Programming for Machine Learning and Data Mining. He received his Ph.D. degree from Rensselaer Polytechnic Institute in 1999. His thesis is titled "Large Margin Classification Methods for Data Mining"
Dr. Wu's research on using SVM for Spam e-mail classification is published in IEEE Transactions on Neural Networks, 5(10):1048-1054, September,1999 (Support Vector Machines for Spam Categorization). His work on extending SVM to decision trees is published in Machine Learning, 41(3): 295-313, December 2000 (Enlarging the Margins in Perceptron Decision Trees). His work on extending SVM and decision for transduction is nominated for best paper award at ICML'99. Proceedings of the 16th International Conference on Machine Learning, ICML'99, p474-483, Morgan Kaufmann, June 1999 (Large Margin Decision Trees for Induction and Transduction(1999)).
by Dr. Premkumar Devanbu
UC Davis
Wednesday, October 24, 2001
Abstract
Programmers working on industrial software systems spend much time examining code and trying to understand it. Code analysis tools can be very useful for this process. However, the best tool in the world isn't going to help you if it's too expensive to use it within your organization. Next time someone wants to sell you a whiz-bang new tool, ask him or her this question: "How many hundredes/thousands of lines of Makefiles and build scripts do I have to change to use your tool?"
If they can't answer this question, run away! We identify "re-targetability" as a key hurdle to the adoption of software tools: can a tool be easily re-targeted to different environments? We describe two tools, GENOA, and CHIME, that are designed to be retargetable. GENOA is a tool-generator that can generate tools to analyze source-code GENOA can be used in conjunction with an existing parser or compiler, and is therefore easier to introduce into an existing development environment. Similarly, CHIME is a tool that can be used to introduce WWW-based source-code browsing into an existing development environment. We describe in detail the motivations behind these tools, the design challenges, the implementation approaches. GENOA is freely downloadable (details at http://seclab.cs.ucdavis.edu/~devanbu/genp).
About the Guest Speaker
Prof. P. Devanbu has been on the faculty at University of California, Davis, since January 1998. Prior to his current appoinment, he was a research staff member at AT&T Laboratories--Research in Florham Park and at AT&T Bell Laboratories, Murray Hill, NJ (prior to the trivestiture). His research interests are in the area of tools for software engineers, particularly for applications in maintenance, reverse engineering, testing, legacy systems, metrics, etc. He is also interested in tools and techniques for security in distributed and mobile systems, and in tool support for converting legacy systems to distributed object standards. Prof P. Devanbu has published papers in the areas of software reuse, software metrics, software tools, security and software engineering. Details of his projects and papers can be seen at http://seclab.cs.ucdavis.edu/~devanbu
by Dr. Pradeep Tapadiya
Hewlett-Packard in Roseville
Wednesday, Nov. 28, 2001
Abstract
The presentation tries to clarify mysteries surrounding .NET. I try to analyze what Microsoft's vision is and what they are doing to achieve this vision. The presentation is fairly non-technical.
About the Guest Speaker
Pradeep Tapadiya is a lead software architect in the OpenView business division of Hewlett-Packard in Roseville, CA and is currently involved in developing a suite of systems management applications for Windows. Pradeep has authored a book titled "COM+ Programming" and is currently writing a book on .NET Programming. Pradeep holds a doctoral degree in computer science from the Texas A&M University, College Station. http://www.tapadiya.net/pradeep
by Dr. Xiangyun Kong
Sun Microsystems in Menlo Park
Wednesday, Feb. 6, 2002
Abstract
Optimizing compilers are keys to computer system performances. All major computer manufacturers have to report their performances with optimizing compilers, and all developers have to use optimizing compilers to develop their applications in order to take full advantage of system performances.
On one aspect, modern optimizing compilers are greatly affected by advances in computer architectures and changes in high level languages. On the other aspect, optimizing compilers technolog also greatly affect on evolution of computer architectures and languages.
In this talk, I will briefly review the current status of optimizing compilers technology, and the trend in the area.
About the Guest Speaker
Xiangyun Kong got his Ph.D. in computer science from Stevens Institute of Technology in 1990. He has been working at Sun Microsystems since then. During working at Sun, he started the Sun's parallelizing compilers project, and designed and implemented major part of Sun's parallelizing compilers. He is currently leading Sun's Compilers Optimizier group.
by Dr. Harry H. Cheng
UC Davis
Wednesday, April 3, 2002
Abstract
The C programming language was originally designed for system programming. It has deficiencies for scientific and engineering applications that require extensive numerical computing. Some deficiencies for numerical computing in the original K&R C had been resolved in C90. However, many severe deficiencies still remain in C90. The latest C standard called C99, ratified in 1999, is a major milestone in evolving C as a leading programming language for scientific numerical computing. Major features added in C99 include IEEE floating-point arithmetic, complex numbers, variable length arrays (VLAs), and generic functions.
In this seminar, these numerical features in C99 will be first presented from design, implementation, and application points of view. Their limitations will be pointed out. Then, a C99/C++ interpreter available from http://www.softintegration.com will be presented. This C99/C++ interpreter has computational arrays as first-class objects, similar to arrays in Fortran 90 and MATLAB, for matrix calculations and numerical analysis. Finally, applications of this C99/C++ interpreter in engineering and computer science for teaching and research in software design, Web-based data acquisition, design and manufacturing, and control of robotic workcells will be presented.
About the Guest Speaker
Dr. Harry H. Cheng is an Associate Professor and the Director of the Integration Engineering Laboratory in the Department of Mechanical and Aeronautical Engineering at the University of California, Davis. His main research interests include engineering software design, Web-based open-architecture design and manufacturing systems, and intelligent transportation systems. He has participated in revision of C99 through ANSI X3J11 and ISO 22/WG14 C Standard Committees since 1993. He has published over 70 technical papers and received one US patent. He is Chair of the technical area of Embedded and Ubiquitous Computing of the ASME Computers in Engineering Division. He received a MS degree in mathematics and a PhD in mechanical engineering from the University of Illinois at Chicago.